DK-DEV-5AGXB3N/ES【PDF 35/39 页】ARRIA V DEVELOPMENT KIT

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AV-51001

2013.12.26

Enhanced Configuration and Configuration via Protocol

35

Apart from lowering cost and power consumption, partial reconfiguration increases the effective logic density

of the device because placing device functions that do not operate simultaneously is not necessary. Instead,

you can store these functions in external memory and load them whenever the functions are required. This

capability reduces the size of the device because it allows multiple applications on a single device — saving

the board space and reducing the power consumption.

Altera simplifies the time-intensive task of partial reconfiguration by building this capability on top of the

proven incremental compile and design flow in the Quartus II design software. With the Altera solution,

you do not need to know all the intricate device architecture details to perform a partial reconfiguration.

Partial reconfiguration is supported through the FPP x16 configuration interface. You can seamlessly use

partial reconfiguration in tandem with dynamic reconfiguration to enable simultaneous partial reconfiguration

of both the device core and transceivers.

Enhanced Configuration and Configuration via Protocol

Table 23: Configuration Modes and Features of Arria V Devices

Arria V devices support 1.8 V, 2.5 V, 3.0 V, and 3.3 V (20) programming voltages and several configuration modes.

Reconfiguration

Mode

Data

Width

Max Clock Max Data Decompression

Rate Rate

Design

Security

Partial

(21)

Remote System

Update

(MHz)

(Mbps)

AS through the

1 bit, 4

100

—

Yes

Yes

—

Yes

EPCS and EPCQ

serial configura-

tion device

bits

PS through CPLD

1 bit

125

125

Yes

Yes

—

—

or external

microcontroller

8 bits

125

—

Yes

Yes

—

FPP

CvP (PCIe)

16 bits

(23)

32 bits

x1, x2, x4,

125

100

—

—

—

—

Yes

Yes

Yes

Yes

Yes

Yes

Yes (22)

—

Yes

Parallel flash loader

—

and x8

lanes

JTAG

Configuration via

HPS

1 bit

16 bits

32 bits

33

125

100

33

—

—

—

Yes

Yes

—

Yes

Yes

—

Yes (22)

—

—

Parallel flash loader

(20)

(21)

(22)

(23)

Arria V GZ does not support 3.3 V.

Partial reconfiguration is an advanced feature of the device family. If you are interested in using partial

reconfiguration, contact Altera for support.

Supported at a clock rate of 50-62.5 MHz.

Arria V GZ only

Arria V Device Overview

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